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authorths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2007-03-30 18:56:19 +0000
committerths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2007-03-30 18:56:19 +0000
commit7246bb21ba7321a0b741405836c24c303c13d268 (patch)
treef7ce622a6bf5ccabdccf08781dd200adc99be46a /target-mips/TODO
parent36bb244bd30faf7ea931bb0ac5ccd76f74f761e4 (diff)
Update mips TODO.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2549 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/TODO')
-rw-r--r--target-mips/TODO6
1 files changed, 1 insertions, 5 deletions
diff --git a/target-mips/TODO b/target-mips/TODO
index 9faa041b2c..c92cbaf970 100644
--- a/target-mips/TODO
+++ b/target-mips/TODO
@@ -6,10 +6,6 @@ General
- [ls][dw][lr] report broken (aligned) BadVAddr
- Missing per-CPU instruction decoding, currently all implemented
instructions are regarded as valid
-- pcnet32 does not work for little endian emulation on big endian host
- (probably not mips specific, but observable for mips-malta)
-- CP1 enable/disable is checked at translation time, not at execution
- time, so it will have delayed effect.
MIPS64
------
@@ -25,4 +21,4 @@ MALTA system emulation
----------------------
- We fake firmware support instead of doing the real thing
- Real firmware falls over when trying to init RAM, presumably due
- to lacking I2C emulation.
+ to lacking system controller emulation.