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authorGreg Bellows <greg.bellows@linaro.org>2015-05-29 11:28:52 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-05-29 11:28:52 +0100
commitc6f191642a4027909813b4e6e288411f8371e951 (patch)
treec2ad623d9938b41924b431ac4b381bf64bc5670c /target-microblaze
parent38836a2cd47c20daaaa84873e3d6020f19e4bfca (diff)
target-arm: Add AArch64 CPTR registers
Adds CPTR_EL2/3 system registers definitions and access function. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: merge CPTR_EL2 and HCPTR definitions into a single def using STATE_BOTH; don't use readfn/writefn to implement RAZ/WI registers; don't use accessfn for the no-EL2 CPTR_EL2; fix cpacr_access logic to catch EL2 accesses to CPACR being trapped to EL3; use new CP_ACCESS_TRAP_EL[23] rather than setting exception.target_el directly] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target-microblaze')
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