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| author | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2009-09-03 12:52:01 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2009-09-03 12:52:01 +0200 |
| commit | 821ebb33e4e3b082b5d1d92b35fa3a9525dc43ce (patch) | |
| tree | 1b810f3a6554282e9c61d0c416a0bf2eeed17d2b /target-microblaze | |
| parent | ee7dbcf8344d826263ccedf57323c4d198a2113f (diff) | |
microblaze: Trap on divizions by zero.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'target-microblaze')
| -rw-r--r-- | target-microblaze/op_helper.c | 7 | ||||
| -rw-r--r-- | target-microblaze/translate.c | 1 |
2 files changed, 6 insertions, 2 deletions
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c index f86b1c78c9..134d243e65 100644 --- a/target-microblaze/op_helper.c +++ b/target-microblaze/op_helper.c @@ -167,7 +167,12 @@ static inline int div_prepare(uint32_t a, uint32_t b) { if (b == 0) { env->sregs[SR_MSR] |= MSR_DZ; - /* FIXME: Raise the div by zero exception. */ + + if ((env->sregs[SR_MSR] & MSR_EE) + && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) { + env->sregs[SR_ESR] = ESR_EC_DIVZERO; + helper_raise_exception(EXCP_HW_EXCP); + } return 0; } env->sregs[SR_MSR] &= ~MSR_DZ; diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index acf3f8db5d..4fbe86a9a9 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -616,7 +616,6 @@ static void dec_div(DisasContext *dc) t_gen_raise_exception(dc, EXCP_HW_EXCP); } - /* FIXME: support div by zero exceptions. */ if (u) gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]); else |