diff options
| author | Paolo Bonzini <pbonzini@redhat.com> | 2014-04-04 08:12:28 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2014-06-05 16:10:34 +0200 |
| commit | 77549a7809c3c9c53dd2573187324ba9d4bd3b42 (patch) | |
| tree | 4e31e8859b458bdc53cd57ae1e8ad11a583ae106 /target-i386 | |
| parent | b052e4509bd4049c25890c56f603995c6763e761 (diff) | |
target-i386: introduce support for 1 GB pages
Given the simplifications to the code in the previous patches, this
is now very simple to do.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target-i386')
| -rw-r--r-- | target-i386/cpu.c | 4 | ||||
| -rw-r--r-- | target-i386/helper.c | 7 |
2 files changed, 8 insertions, 3 deletions
diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 042a48d703..0f400d4011 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -569,9 +569,7 @@ struct X86CPUDefinition { CPUID_EXT_RDRAND */ #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ - CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT) - /* missing: - CPUID_EXT2_PDPE1GB */ + CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB) #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) #define TCG_SVM_FEATURES 0 diff --git a/target-i386/helper.c b/target-i386/helper.c index d09e1c8ba8..5a5036494b 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -605,6 +605,13 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, pdpe |= PG_ACCESSED_MASK; stl_phys_notdirty(cs->as, pdpe_addr, pdpe); } + if (pdpe & PG_PSE_MASK) { + /* 1 GB page */ + page_size = 1024 * 1024 * 1024; + pte_addr = pdpe_addr; + pte = pdpe; + goto do_check_protect; + } } else #endif { |