diff options
| author | Richard Henderson <rth@twiddle.net> | 2013-11-02 08:16:45 -1000 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2014-01-07 11:36:31 -0800 |
| commit | ee3138da2f76b415cbce6466aa4083a84fc26241 (patch) | |
| tree | ace6bb5c5529b3d5250cb7378338f6c410646128 /target-i386 | |
| parent | b5afc104947369cd3d49de88dee8629193639b46 (diff) | |
target-i386: Fix typo in gen_push_T1
By inspection, obviously we should be storing T[1] not T[0].
This could only happen for x86_64 in 64-bit mode with 0x66
prefix to call insn -- i.e. never.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-i386')
| -rw-r--r-- | target-i386/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c index a1a23a6c90..9205b72da0 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -2488,7 +2488,7 @@ static void gen_push_T1(DisasContext *s) gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0); } else { gen_op_addq_A0_im(-2); - gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); + gen_op_st_v(s, MO_16, cpu_T[1], cpu_A0); } gen_op_mov_reg_A0(2, R_ESP); } else |