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authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2005-01-06 20:44:11 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2005-01-06 20:44:11 +0000
commit826461bb4068bab1c8fef6eb11117a260aa3e2c0 (patch)
treebe17fcc311279623b8c5bf9eb0adf30a88665a49 /target-i386
parent02536f8b1f94a701ac3ef8016741fe01cc68cff2 (diff)
big endian SSE fix
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1201 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386')
-rw-r--r--target-i386/cpu.h41
1 files changed, 33 insertions, 8 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 883236386e..e65fc2e2ce 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -339,15 +339,40 @@ typedef struct SegmentCache {
uint32_t flags;
} SegmentCache;
-typedef struct {
- union {
- uint8_t b[16];
- uint16_t w[8];
- uint32_t l[4];
- uint64_t q[2];
- } u;
+typedef union {
+ uint8_t _b[16];
+ uint16_t _w[8];
+ uint32_t _l[4];
+ uint64_t _q[2];
} XMMReg;
+typedef union {
+ uint8_t _b[8];
+ uint16_t _w[2];
+ uint32_t _l[1];
+ uint64_t q;
+} MMXReg;
+
+#ifdef WORDS_BIGENDIAN
+#define XMM_B(n) _b[15 - (n)]
+#define XMM_W(n) _w[7 - (n)]
+#define XMM_L(n) _l[3 - (n)]
+#define XMM_Q(n) _q[1 - (n)]
+
+#define MMX_B(n) _b[7 - (n)]
+#define MMX_W(n) _w[3 - (n)]
+#define MMX_L(n) _l[1 - (n)]
+#else
+#define XMM_B(n) _b[n]
+#define XMM_W(n) _w[n]
+#define XMM_L(n) _l[n]
+#define XMM_Q(n) _q[n]
+
+#define MMX_B(n) _b[n]
+#define MMX_W(n) _w[n]
+#define MMX_L(n) _l[n]
+#endif
+
#ifdef TARGET_X86_64
#define CPU_NB_REGS 16
#else
@@ -425,7 +450,7 @@ typedef struct CPUX86State {
int exception_index;
int error_code;
int exception_is_int;
- int exception_next_eip;
+ target_ulong exception_next_eip;
struct TranslationBlock *current_tb; /* currently executing TB */
target_ulong cr[5]; /* NOTE: cr1 is unused */
target_ulong dr[8]; /* debug registers */