Core 2 Duo specification (Alexander Graf).

This patch adds a Core 2 Duo CPU to the available CPU types. The CPU
definition tries to resemble a real CPU as good as possible, whilst not
exposing features qemu does not implement.
The patch also includes some minor additions that Core 2 Duo CPUs have:

- New MSR: MSR_IA32_PERF_STATUS
- CPUID up to level 5 (cache info and mwait)

Signed-off-by: Alexander Graf <agraf@suse.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5317 c046a42c-6fe2-441c-8c8c-71466251a162

1 files changed, 43 insertions, 0 deletions

diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index 23f3080905..c423ca05d4 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -1919,6 +1919,43 @@ void helper_cpuid(void)
         ECX = 0;
         EDX = 0x2c307d;
         break;
+    case 4:
+        /* cache info: needed for Core compatibility */
+        switch (ECX) {
+            case 0: /* L1 dcache info */
+                EAX = 0x0000121;
+                EBX = 0x1c0003f;
+                ECX = 0x000003f;
+                EDX = 0x0000001;
+                break;
+            case 1: /* L1 icache info */
+                EAX = 0x0000122;
+                EBX = 0x1c0003f;
+                ECX = 0x000003f;
+                EDX = 0x0000001;
+                break;
+            case 2: /* L2 cache info */
+                EAX = 0x0000143;
+                EBX = 0x3c0003f;
+                ECX = 0x0000fff;
+                EDX = 0x0000001;
+                break;
+            default: /* end of info */
+                EAX = 0;
+                EBX = 0;
+                ECX = 0;
+                EDX = 0;
+                break;
+        }
+
+        break;
+    case 5:
+        /* mwait info: needed for Core compatibility */
+        EAX = 0; /* Smallest monitor-line size in bytes */
+        EBX = 0; /* Largest monitor-line size in bytes */
+        ECX = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
+        EDX = 0;
+        break;
     case 0x80000000:
         EAX = env->cpuid_xlevel;
         EBX = env->cpuid_vendor1;
@@ -3089,6 +3126,12 @@ void helper_wrmsr(void)
     case MSR_VM_HSAVE_PA:
         env->vm_hsave = val;
         break;
+    case MSR_IA32_PERF_STATUS:
+        /* tsc_increment_by_tick */ 
+        val = 1000ULL;
+        /* CPU multiplier */
+        val |= (((uint64_t)4ULL) << 40);
+        break;
 #ifdef TARGET_X86_64
     case MSR_LSTAR:
         env->lstar = val;