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authorBlue Swirl <blauwirbel@gmail.com>2010-06-19 10:42:31 +0300
committerBlue Swirl <blauwirbel@gmail.com>2010-06-19 10:42:31 +0300
commit4a942ceac7e38c259116960e45ba9619611d1df9 (patch)
treeec382b627110dc208da9e179cebe323f529e3d1c /target-i386/op_helper.c
parentcf6d64bfd9ae93d14502f057d8a0917162004dc7 (diff)
apic: avoid passing CPUState from CPU code
Pass only APICState when accessing APIC from CPU code. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-i386/op_helper.c')
-rw-r--r--target-i386/op_helper.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index dcbdfe7e0b..c1256f4abd 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -2888,7 +2888,7 @@ target_ulong helper_read_crN(int reg)
break;
case 8:
if (!(env->hflags2 & HF2_VINTR_MASK)) {
- val = cpu_get_apic_tpr(env);
+ val = cpu_get_apic_tpr(env->apic_state);
} else {
val = env->v_tpr;
}
@@ -2912,7 +2912,7 @@ void helper_write_crN(int reg, target_ulong t0)
break;
case 8:
if (!(env->hflags2 & HF2_VINTR_MASK)) {
- cpu_set_apic_tpr(env, t0);
+ cpu_set_apic_tpr(env->apic_state, t0);
}
env->v_tpr = t0 & 0x0f;
break;
@@ -3020,7 +3020,7 @@ void helper_wrmsr(void)
env->sysenter_eip = val;
break;
case MSR_IA32_APICBASE:
- cpu_set_apic_base(env, val);
+ cpu_set_apic_base(env->apic_state, val);
break;
case MSR_EFER:
{
@@ -3153,7 +3153,7 @@ void helper_rdmsr(void)
val = env->sysenter_eip;
break;
case MSR_IA32_APICBASE:
- val = cpu_get_apic_base(env);
+ val = cpu_get_apic_base(env->apic_state);
break;
case MSR_EFER:
val = env->efer;