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authorpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-29 13:55:36 +0000
committerpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-29 13:55:36 +0000
commit558fa8361bc3e35fce73448c0b45e9d85ab59130 (patch)
tree1f8016969030e304d40d044b40a7e79fb44a1985 /target-i386/op_helper.c
parente6a6d5abc680ab7872c0faeb91326654379c12cf (diff)
My core2duo patch introduced a vague statement of "missing features" in
the CPUID specification. This patch addresses this by specifying exactly what is missing. While going along the missing CPUID entries I also stumbled across invalid and missing CPUID #defines while comparing them to the Intel Documentation. This patch also addresses these. I found them too minor to split them up in a separate patch. Furthermore I looked through CPUID functions > 5 and realized that it should be safe to bump the level to 10. I tried booting Linux with that and it worked fine. Signed-off-by: Alexander Graf <agraf@suse.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5350 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386/op_helper.c')
-rw-r--r--target-i386/op_helper.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index 74167f4809..737056ae75 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -1956,6 +1956,27 @@ void helper_cpuid(void)
ECX = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
EDX = 0;
break;
+ case 6:
+ /* Thermal and Power Leaf */
+ EAX = 0;
+ EBX = 0;
+ ECX = 0;
+ EDX = 0;
+ break;
+ case 9:
+ /* Direct Cache Access Information Leaf */
+ EAX = 0; /* Bits 0-31 in DCA_CAP MSR */
+ EBX = 0;
+ ECX = 0;
+ EDX = 0;
+ break;
+ case 0xA:
+ /* Architectural Performance Monitoring Leaf */
+ EAX = 0;
+ EBX = 0;
+ ECX = 0;
+ EDX = 0;
+ break;
case 0x80000000:
EAX = env->cpuid_xlevel;
EBX = env->cpuid_vendor1;