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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-02-15 11:45:11 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-02-15 11:45:11 +0000 |
| commit | 80b5d6bfc1280fa06e2514a414690c0e5b4b514b (patch) | |
| tree | 5df97c0cda565f1a3156b6dd6c60a8ea0902cf30 /target-i386/misc_helper.c | |
| parent | a5af12871fd4601c44f08d9e49131e9ca13ef102 (diff) | |
| parent | 07929f2ab2ab9c9e01d4ae79f48f2b2476b715c8 (diff) | |
Merge remote-tracking branch 'remotes/rth/tags/pull-i386-20160215' into staging
Add XSAVE, MPX, FSGSBASE.
# gpg: Signature made Mon 15 Feb 2016 11:21:50 GMT using RSA key ID 4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg: aka "Richard Henderson <rth@redhat.com>"
# gpg: aka "Richard Henderson <rth@twiddle.net>"
* remotes/rth/tags/pull-i386-20160215:
target-i386: Implement FSGSBASE
target-i386: Enable CR4/XCR0 features for user-mode
target-i386: Clear bndregs during legacy near jumps
target-i386: Implement BNDLDX, BNDSTX
target-i386: Update BNDSTATUS for exceptions raised by BOUND
target-i386: Implement BNDCL, BNDCU, BNDCN
target-i386: Implement BNDMOV
target-i386: Implement BNDMK
target-i386: Split up gen_lea_modrm
target-i386: Perform set/reset_inhibit_irq inline
target-i386: Enable control registers for MPX
target-i386: Implement XSAVEOPT
target-i386: Add XSAVE extension
target-i386: Rearrange processing of 0F AE
target-i386: Rearrange processing of 0F 01
target-i386: Split fxsave/fxrstor implementation
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-i386/misc_helper.c')
| -rw-r--r-- | target-i386/misc_helper.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c index 460257f6bc..5fbab8fd0c 100644 --- a/target-i386/misc_helper.c +++ b/target-i386/misc_helper.c @@ -361,6 +361,12 @@ void helper_wrmsr(CPUX86State *env) case MSR_IA32_MISC_ENABLE: env->msr_ia32_misc_enable = val; break; + case MSR_IA32_BNDCFGS: + /* FIXME: #GP if reserved bits are set. */ + /* FIXME: Extend highest implemented bit of linear address. */ + env->msr_bndcfgs = val; + cpu_sync_bndcs_hflags(env); + break; default: if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + @@ -506,6 +512,9 @@ void helper_rdmsr(CPUX86State *env) case MSR_IA32_MISC_ENABLE: val = env->msr_ia32_misc_enable; break; + case MSR_IA32_BNDCFGS: + val = env->msr_bndcfgs; + break; default: if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + |