diff options
| author | Dr. David Alan Gilbert <dgilbert@redhat.com> | 2016-09-22 14:49:17 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2016-09-22 17:25:59 +0200 |
| commit | f8d9ccf8d5f9f4b7d364100871c4c7303b546de5 (patch) | |
| tree | d20c18fe7e24a010e0c8693e412b4c302053727b /target-i386/kvm.c | |
| parent | 73e1b8f2f9b8a90361f9c1af306ee17bfcfd592d (diff) | |
kvm: apic: set APIC base as part of kvm_apic_put
The parsing of KVM_SET_LAPIC's input depends on the current value of the
APIC base MSR---which indeed is stored in APICCommonState---but for historical
reasons APIC base is set through KVM_SET_SREGS together with cr8 (which is
really just the APIC TPR) and the actual "special CPU registers".
APIC base must now be set before the actual LAPIC registers, so do that
in kvm_apic_put. It will be set again to the same value with KVM_SET_SREGS,
but that's not a big issue.
This only happens since Linux 4.8, which checks for x2apic mode in
KVM_SET_LAPIC. However it's really a QEMU bug; until the recent
commit 78d6a05 ("x86/lapic: Load LAPIC state at post_load", 2016-09-13)
QEMU was indeed setting APIC base (via KVM_SET_SREGS) before the other
LAPIC registers.
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target-i386/kvm.c')
| -rw-r--r-- | target-i386/kvm.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target-i386/kvm.c b/target-i386/kvm.c index c57b01b558..f236dafae5 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -1540,6 +1540,14 @@ static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value) return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); } +void kvm_put_apicbase(X86CPU *cpu, uint64_t value) +{ + int ret; + + ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value); + assert(ret == 1); +} + static int kvm_put_tscdeadline_msr(X86CPU *cpu) { CPUX86State *env = &cpu->env; |