diff options
| author | liguang <lig.fnst@cn.fujitsu.com> | 2013-01-15 13:39:55 +0800 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-01-15 09:14:35 +0100 |
| commit | 428065ce50643a56bff043501809b62b035f0b17 (patch) | |
| tree | 0e854bab9efea8205eae804dd5a3c5860e2c40e7 /target-i386/helper.c | |
| parent | 5ec01c2e96910e1588d1a0de8609b9dda7618c7f (diff) | |
target-i386: Define DR7 bit field constants
Implicit use of dr7 bit field is a little hard to understand,
so define constants for them and use them consistently.
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-i386/helper.c')
| -rw-r--r-- | target-i386/helper.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/target-i386/helper.c b/target-i386/helper.c index fa622e114d..1fceb91d34 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -969,18 +969,18 @@ void hw_breakpoint_insert(CPUX86State *env, int index) int type, err = 0; switch (hw_breakpoint_type(env->dr[7], index)) { - case 0: + case DR7_TYPE_BP_INST: if (hw_breakpoint_enabled(env->dr[7], index)) err = cpu_breakpoint_insert(env, env->dr[index], BP_CPU, &env->cpu_breakpoint[index]); break; - case 1: + case DR7_TYPE_DATA_WR: type = BP_CPU | BP_MEM_WRITE; goto insert_wp; - case 2: + case DR7_TYPE_IO_RW: /* No support for I/O watchpoints yet */ break; - case 3: + case DR7_TYPE_DATA_RW: type = BP_CPU | BP_MEM_ACCESS; insert_wp: err = cpu_watchpoint_insert(env, env->dr[index], @@ -997,15 +997,15 @@ void hw_breakpoint_remove(CPUX86State *env, int index) if (!env->cpu_breakpoint[index]) return; switch (hw_breakpoint_type(env->dr[7], index)) { - case 0: + case DR7_TYPE_BP_INST: if (hw_breakpoint_enabled(env->dr[7], index)) cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[index]); break; - case 1: - case 3: + case DR7_TYPE_DATA_WR: + case DR7_TYPE_DATA_RW: cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[index]); break; - case 2: + case DR7_TYPE_IO_RW: /* No support for I/O watchpoints yet */ break; } @@ -1018,7 +1018,7 @@ int check_hw_breakpoints(CPUX86State *env, int force_dr6_update) int hit_enabled = 0; dr6 = env->dr[6] & ~0xf; - for (reg = 0; reg < 4; reg++) { + for (reg = 0; reg < DR7_MAX_BP; reg++) { type = hw_breakpoint_type(env->dr[7], reg); if ((type == 0 && env->dr[reg] == env->eip) || ((type & 1) && env->cpu_watchpoint[reg] && |