diff options
author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2004-02-03 23:28:30 +0000 |
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committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2004-02-03 23:28:30 +0000 |
commit | 1ac157da77c863b62b1d2f467626a440d57cf17d (patch) | |
tree | e30f993b2039e69399024d24069a6c9770e3022e /target-i386/helper.c | |
parent | 64a595f26ae04ee386a3ce725c9222535dc28022 (diff) |
more precise TLB invalidation - init cleanup
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@596 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386/helper.c')
-rw-r--r-- | target-i386/helper.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/target-i386/helper.c b/target-i386/helper.c index b33d9cf1ee..9a980bd9d5 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -424,8 +424,7 @@ static void switch_tss(int tss_selector, env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK; if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) { - env->cr[3] = new_cr3; - cpu_x86_update_cr3(env); + cpu_x86_update_cr3(env, new_cr3); } /* load all registers without an exception, then reload them with @@ -1775,13 +1774,18 @@ void helper_lret_protected(int shift, int addend) void helper_movl_crN_T0(int reg) { - env->cr[reg] = T0; switch(reg) { case 0: - cpu_x86_update_cr0(env); + cpu_x86_update_cr0(env, T0); break; case 3: - cpu_x86_update_cr3(env); + cpu_x86_update_cr3(env, T0); + break; + case 4: + cpu_x86_update_cr4(env, T0); + break; + default: + env->cr[reg] = T0; break; } } |