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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-07-06 11:04:54 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-07-06 11:04:54 +0100 |
| commit | 261ccf426a6df854ba398be92413476919dd67f9 (patch) | |
| tree | e72d79039c7a01270f4869331f5aecd2840dc264 /target-i386/cpu.h | |
| parent | f50a1640fb82708a5d528dee1ace42a224b95b15 (diff) | |
| parent | 257621a9566054472d1d55a819880d0f9da02bda (diff) | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150706' into staging
target-arm queue:
* TLBI ALLEI1IS should operate on all CPUs, not just this one
* Fix interval interrupt of cadence ttc in decrement mode
* Implement YIELD insn to yield in ARM and Thumb translators
* ARM GIC: reset all registers
* arm_mptimer: fix timer shutdown and mode change
* arm_mptimer: respect IT bit state
# gpg: Signature made Mon Jul 6 10:58:27 2015 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
* remotes/pmaydell/tags/pull-target-arm-20150706:
arm_mptimer: Respect IT bit state
arm_mptimer: Fix timer shutdown and mode change
hw/intc/arm_gic_common.c: Reset all registers
target-arm: Implement YIELD insn to yield in ARM and Thumb translators
target-arm: Split DISAS_YIELD from DISAS_WFE
Fix interval interrupt of cadence ttc when timer is in decrement mode
target-arm: fix write helper for TLBI ALLE1IS
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-i386/cpu.h')
0 files changed, 0 insertions, 0 deletions