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authorXiao Guangrong <guangrong.xiao@linux.intel.com>2015-10-29 15:31:39 +0800
committerEduardo Habkost <ehabkost@redhat.com>2015-11-05 17:35:04 -0200
commitf7fda280948a5e74aeb076ef346b991ecb173c56 (patch)
tree399a589a31e92ff01bdff294acb99f07f58d822d /target-i386/cpu.h
parent6aa91e4a0237ddcebb85e3a95e166f3b3cfa42ae (diff)
target-i386: Enable clflushopt/clwb/pcommit instructions
These instructions are used by NVDIMM drivers and the specification is located at: https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf There instructions are available on Skylake Server. Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'target-i386/cpu.h')
-rw-r--r--target-i386/cpu.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 62f78798b6..fc4a605d6a 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -576,6 +576,9 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EBX_RDSEED (1U << 18)
#define CPUID_7_0_EBX_ADX (1U << 19)
#define CPUID_7_0_EBX_SMAP (1U << 20)
+#define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */
+#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
+#define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */
#define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
#define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
#define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */