diff options
| author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-25 18:11:30 +0000 |
|---|---|---|
| committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-25 18:11:30 +0000 |
| commit | e737b32a3688d415c3b1f9d0a3fb2b941b1e758c (patch) | |
| tree | 821be1b667f4d9430bbb89af4697b99536b0ce98 /target-i386/cpu.h | |
| parent | c5096daf7f5e6d8a607319fbd1dfa8acbe96f4b8 (diff) | |
Core 2 Duo specification (Alexander Graf).
This patch adds a Core 2 Duo CPU to the available CPU types. The CPU
definition tries to resemble a real CPU as good as possible, whilst not
exposing features qemu does not implement.
The patch also includes some minor additions that Core 2 Duo CPUs have:
- New MSR: MSR_IA32_PERF_STATUS
- CPUID up to level 5 (cache info and mwait)
Signed-off-by: Alexander Graf <agraf@suse.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5317 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386/cpu.h')
| -rw-r--r-- | target-i386/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index dd57abcecc..d1deda7197 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -242,6 +242,8 @@ #define MSR_MCG_STATUS 0x17a #define MSR_MCG_CTL 0x17b +#define MSR_IA32_PERF_STATUS 0x198 + #define MSR_PAT 0x277 #define MSR_EFER 0xc0000080 @@ -341,6 +343,9 @@ #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ +#define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ +#define CPUID_MWAIT_EMX (0 << 1) /* enumeration supported */ + #define EXCP00_DIVZ 0 #define EXCP01_SSTP 1 #define EXCP02_NMI 2 |