diff options
| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-08 13:28:47 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-08 13:28:47 +0000 |
| commit | a049de6161feb4d62bdd962401d3e35ebf4331dc (patch) | |
| tree | 3cf3afc495096ee96a5adfb0d6ad193e2b12f950 /target-i386/cpu.h | |
| parent | 5fa0ab8fcbd25bbb72f51f923f0595e05f091476 (diff) | |
added -cpu option for x86 (initial patch by Dan Kenigsberg)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3547 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386/cpu.h')
| -rw-r--r-- | target-i386/cpu.h | 39 |
1 files changed, 38 insertions, 1 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 23419909cf..e92fc31048 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -274,23 +274,56 @@ #define CPUID_CMOV (1 << 15) #define CPUID_PAT (1 << 16) #define CPUID_PSE36 (1 << 17) +#define CPUID_PN (1 << 18) #define CPUID_CLFLUSH (1 << 19) -/* ... */ +#define CPUID_DTS (1 << 21) +#define CPUID_ACPI (1 << 22) #define CPUID_MMX (1 << 23) #define CPUID_FXSR (1 << 24) #define CPUID_SSE (1 << 25) #define CPUID_SSE2 (1 << 26) +#define CPUID_SS (1 << 27) +#define CPUID_HT (1 << 28) +#define CPUID_TM (1 << 29) +#define CPUID_IA64 (1 << 30) +#define CPUID_PBE (1 << 31) #define CPUID_EXT_SSE3 (1 << 0) #define CPUID_EXT_MONITOR (1 << 3) +#define CPUID_EXT_DSCPL (1 << 4) +#define CPUID_EXT_VMX (1 << 5) +#define CPUID_EXT_SMX (1 << 6) +#define CPUID_EXT_EST (1 << 7) +#define CPUID_EXT_TM2 (1 << 8) +#define CPUID_EXT_SSSE3 (1 << 9) +#define CPUID_EXT_CID (1 << 10) #define CPUID_EXT_CX16 (1 << 13) +#define CPUID_EXT_XTPR (1 << 14) +#define CPUID_EXT_DCA (1 << 17) +#define CPUID_EXT_POPCNT (1 << 22) #define CPUID_EXT2_SYSCALL (1 << 11) +#define CPUID_EXT2_MP (1 << 19) #define CPUID_EXT2_NX (1 << 20) +#define CPUID_EXT2_MMXEXT (1 << 22) #define CPUID_EXT2_FFXSR (1 << 25) +#define CPUID_EXT2_PDPE1GB (1 << 26) +#define CPUID_EXT2_RDTSCP (1 << 27) #define CPUID_EXT2_LM (1 << 29) +#define CPUID_EXT2_3DNOWEXT (1 << 30) +#define CPUID_EXT2_3DNOW (1 << 31) +#define CPUID_EXT3_LAHF_LM (1 << 0) +#define CPUID_EXT3_CMP_LEG (1 << 1) #define CPUID_EXT3_SVM (1 << 2) +#define CPUID_EXT3_EXTAPIC (1 << 3) +#define CPUID_EXT3_CR8LEG (1 << 4) +#define CPUID_EXT3_ABM (1 << 5) +#define CPUID_EXT3_SSE4A (1 << 6) +#define CPUID_EXT3_MISALIGNSSE (1 << 7) +#define CPUID_EXT3_3DNOWPREFETCH (1 << 8) +#define CPUID_EXT3_OSVW (1 << 9) +#define CPUID_EXT3_IBS (1 << 10) #define EXCP00_DIVZ 0 #define EXCP01_SSTP 1 @@ -566,6 +599,9 @@ typedef struct CPUX86State { CPUX86State *cpu_x86_init(void); int cpu_x86_exec(CPUX86State *s); void cpu_x86_close(CPUX86State *s); +int x86_find_cpu_by_name (const unsigned char *name); +void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, + ...)); int cpu_get_pic_interrupt(CPUX86State *s); /* MSDOS compatibility mode FPU exception support */ void cpu_set_ferr(CPUX86State *s); @@ -689,6 +725,7 @@ static inline int cpu_get_time_fast(void) #define cpu_exec cpu_x86_exec #define cpu_gen_code cpu_x86_gen_code #define cpu_signal_handler cpu_x86_signal_handler +#define cpu_list x86_cpu_list /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel |