diff options
| author | Liu, Jinsong <jinsong.liu@intel.com> | 2011-10-05 16:52:32 -0300 |
|---|---|---|
| committer | Marcelo Tosatti <mtosatti@redhat.com> | 2011-10-24 21:29:07 -0200 |
| commit | aa82ba549a3a88f7215e65956f3cb4bfd34835cc (patch) | |
| tree | 17a5b466b28f22e949482600d1a0c66ae73cea32 /target-i386/cpu.h | |
| parent | 38d2c27ea68468bd2fdaa19c74d9e6d290f94777 (diff) | |
kvm: support TSC deadline MSR with subsection
KVM add emulation of lapic tsc deadline timer for guest.
This patch is co-operation work at qemu side.
Use subsections to save/restore the field (mtosatti).
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Diffstat (limited to 'target-i386/cpu.h')
| -rw-r--r-- | target-i386/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index ae36489a9a..29412dc523 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -283,6 +283,7 @@ #define MSR_IA32_APICBASE_BSP (1<<8) #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_BASE (0xfffff<<12) +#define MSR_IA32_TSCDEADLINE 0x6e0 #define MSR_MTRRcap 0xfe #define MSR_MTRRcap_VCNT 8 @@ -687,6 +688,7 @@ typedef struct CPUX86State { uint64_t async_pf_en_msr; uint64_t tsc; + uint64_t tsc_deadline; uint64_t mcg_status; |