diff options
| author | Will Auld <will.auld.intel@gmail.com> | 2012-11-26 21:32:18 -0800 |
|---|---|---|
| committer | Marcelo Tosatti <mtosatti@redhat.com> | 2012-12-14 18:17:36 -0200 |
| commit | f28558d3d37ad3bc4e35e8ac93f7bf81a0d5622c (patch) | |
| tree | b9739616a21b467712f6e212559b4ee5a68e3b0d /target-i386/cpu.h | |
| parent | e376a788ae130454ad5e797f60cb70d0308babb6 (diff) | |
target-i386: Enabling IA32_TSC_ADJUST for QEMU KVM guest VMs
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to the
hypervisor vcpu specific locations to store the value of the emulated MSRs.
In this way the IA32_TSC_ADJUST value will be included in all reads to
the TSC MSR whether through rdmsr or rdtsc.
As this is a new MSR that the guest may access and modify its value needs
to be migrated along with the other MRSs. The changes here are specifically
for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added
for migrating its value.
Signed-off-by: Will Auld <will.auld@intel.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Diffstat (limited to 'target-i386/cpu.h')
| -rw-r--r-- | target-i386/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 386c4f6d98..477da33aa8 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -295,6 +295,7 @@ #define MSR_IA32_APICBASE_BSP (1<<8) #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_BASE (0xfffff<<12) +#define MSR_TSC_ADJUST 0x0000003b #define MSR_IA32_TSCDEADLINE 0x6e0 #define MSR_MTRRcap 0xfe @@ -774,6 +775,7 @@ typedef struct CPUX86State { uint64_t pv_eoi_en_msr; uint64_t tsc; + uint64_t tsc_adjust; uint64_t tsc_deadline; uint64_t mcg_status; |