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| author | Anthony Liguori <aliguori@us.ibm.com> | 2011-10-31 11:00:27 -0500 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2011-10-31 11:00:27 -0500 |
| commit | 549f808b577c7709aeaa0244972d3ae28fad97d2 (patch) | |
| tree | 8b550be7aa7a46b083595a11db853d64bad93436 /target-i386/cpu.h | |
| parent | 3a069ff11b9178a84f560435b2fd22294d839018 (diff) | |
| parent | 21e87c4625f290824f4f05d098e576cda40421ce (diff) | |
Merge remote-tracking branch 'qemu-kvm-tmp/uq/master' into staging
Diffstat (limited to 'target-i386/cpu.h')
| -rw-r--r-- | target-i386/cpu.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index a973f2e20c..a08ce9d873 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -300,6 +300,10 @@ #define MSR_IA32_PERF_STATUS 0x198 +#define MSR_IA32_MISC_ENABLE 0x1a0 +/* Indicates good rep/movs microcode on some processors: */ +#define MSR_IA32_MISC_ENABLE_DEFAULT 1 + #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) @@ -691,6 +695,7 @@ typedef struct CPUX86State { uint64_t tsc_deadline; uint64_t mcg_status; + uint64_t msr_ia32_misc_enable; /* exception/interrupt handling */ int error_code; @@ -949,7 +954,7 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define cpu_list_id x86_cpu_list #define cpudef_setup x86_cpudef_setup -#define CPU_SAVE_VERSION 13 +#define CPU_SAVE_VERSION 12 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel |