diff options
| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-11-23 21:02:10 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-11-23 21:02:10 +0000 |
| commit | d2ac63e03e21b1a4be24615792b36ec4e953333b (patch) | |
| tree | 4dcd248560300dd529d9a84d4ce58d1db56212fe /target-i386/cpu.h | |
| parent | ad49ff9de3f15d1b91416ecd005cfae16aba0026 (diff) | |
added HF_HALTED bit
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1651 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386/cpu.h')
| -rw-r--r-- | target-i386/cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index cd12ca17ed..068ebcddb0 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -116,7 +116,7 @@ #define ID_MASK 0x00200000 /* hidden flags - used internally by qemu to represent additionnal cpu - states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid + states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring with eflags. */ /* current cpl */ @@ -141,6 +141,7 @@ #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ #define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */ #define HF_VM_SHIFT 17 /* must be same as eflags */ +#define HF_HALTED_SHIFT 18 /* CPU halted */ #define HF_CPL_MASK (3 << HF_CPL_SHIFT) #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) @@ -156,6 +157,7 @@ #define HF_LMA_MASK (1 << HF_LMA_SHIFT) #define HF_CS64_MASK (1 << HF_CS64_SHIFT) #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) +#define HF_HALTED_MASK (1 << HF_HALTED_SHIFT) #define CR0_PE_MASK (1 << 0) #define CR0_MP_MASK (1 << 1) |