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authorPaolo Bonzini <pbonzini@redhat.com>2013-03-12 13:16:28 +0100
committerPaolo Bonzini <pbonzini@redhat.com>2014-05-13 13:12:40 +0200
commit43175fa96add507afee6c0a83ec9ffe0ca130fc3 (patch)
tree3b720e0bcd3c0d806f0276bf8e38f9943bb38ee2 /target-i386/cpu.c
parent05e7e819d7d159a75a46354aead95e1199b8f168 (diff)
target-i386: preserve FPU and MSR state on INIT
Most MSRs, plus the FPU, MMX, MXCSR, XMM and YMM registers should not be zeroed on INIT (Table 9-1 in the Intel SDM). Copy them out of CPUX86State and back in, instead of special casing env->pat. The relevant fields are already consecutive except PAT and SMBASE. However: - KVM and Hyper-V MSRs should be reset because they include memory locations written by the hypervisor. These MSRs are moved together at the end of the preserved area. - SVM state can be moved out of the way since it is written by VMRUN. Cc: Andreas Faerber <afaerber@suse.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target-i386/cpu.c')
-rw-r--r--target-i386/cpu.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 79b1bb92f0..042a48d703 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2418,8 +2418,7 @@ static void x86_cpu_reset(CPUState *s)
xcc->parent_reset(s);
-
- memset(env, 0, offsetof(CPUX86State, pat));
+ memset(env, 0, offsetof(CPUX86State, cpuid_level));
tlb_flush(s, 1);