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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-01-21 15:00:39 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-01-21 15:00:39 +0000 |
| commit | 1a4f446f81c63151efc30f3ce60a749e8a4cf680 (patch) | |
| tree | 7fb7c5695aad485d9a3a3830177493afb9c704ee /target-i386/cpu.c | |
| parent | 3c9331c47f22224118d5019b0af8eac704824d8d (diff) | |
| parent | 03fbf20f4da58f41998dc10ec7542f65d37ba759 (diff) | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160121' into staging
target-arm queue:
* connect SPI devices in Xilinx Zynq platforms
* multiple-address-space support
* use multiple-address-space support for ARM TrustZone
* arm_gic: return correct ID registers for 11MPCore/v1/v2 GICs
* various fixes for (currently disabled) AArch64 EL2 and EL3 support
* add 'always-on' property to the virt board timer DT entry
# gpg: Signature made Thu 21 Jan 2016 14:54:56 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
* remotes/pmaydell/tags/pull-target-arm-20160121: (36 commits)
target-arm: Implement FPEXC32_EL2 system register
target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode
target-arm: Implement remaining illegal return event checks
target-arm: Handle exception return from AArch64 to non-EL0 AArch32
target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target
target-arm: Pull semihosting handling out to arm_cpu_do_interrupt()
target-arm: Use a single entry point for AArch64 and AArch32 exceptions
target-arm: Move aarch64_cpu_do_interrupt() to helper.c
target-arm: Properly support EL2 and EL3 in arm_el_is_aa64()
arm_gic: Update ID registers based on revision
hw/arm/virt: Add always-on property to the virt board timer
hw/arm/virt: add secure memory region and UART
hw/arm/virt: Wire up memory region to CPUs explicitly
target-arm: Support multiple address spaces in page table walks
target-arm: Implement cpu_get_phys_page_attrs_debug
target-arm: Implement asidx_from_attrs
target-arm: Add QOM property for Secure memory region
qom/cpu: Add MemoryRegion property
memory: Add address_space_init_shareable()
exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-i386/cpu.c')
| -rw-r--r-- | target-i386/cpu.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 0d447b5690..4430494085 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2861,9 +2861,10 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY if (tcg_enabled()) { + AddressSpace *newas = g_new(AddressSpace, 1); + cpu->cpu_as_mem = g_new(MemoryRegion, 1); cpu->cpu_as_root = g_new(MemoryRegion, 1); - cs->as = g_new(AddressSpace, 1); /* Outer container... */ memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull); @@ -2876,7 +2877,9 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) get_system_memory(), 0, ~0ull); memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0); memory_region_set_enabled(cpu->cpu_as_mem, true); - address_space_init(cs->as, cpu->cpu_as_root, "CPU"); + address_space_init(newas, cpu->cpu_as_root, "CPU"); + cs->num_ases = 1; + cpu_address_space_init(cs, newas, 0); /* ... SMRAM with higher priority, linked from /machine/smram. */ cpu->machine_done.notify = x86_cpu_machine_done; |