diff options
| author | Paolo Bonzini <pbonzini@redhat.com> | 2014-04-29 13:10:05 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2014-05-13 13:12:40 +0200 |
| commit | 05e7e819d7d159a75a46354aead95e1199b8f168 (patch) | |
| tree | 21d3a16f818fc2b43c7333d870eff76fde1a8a07 /target-i386/cpu.c | |
| parent | e0723c451028102d9165e21424b4833376ce9666 (diff) | |
target-i386: fix set of registers zeroed on reset
BND0-3, BNDCFGU, BNDCFGS, BNDSTATUS were not zeroed on reset, but they
should be (Intel Instruction Set Extensions Programming Reference
319433-015, pages 9-4 and 9-6). Same for YMM.
XCR0 should be reset to 1.
TSC and TSC_RESET were zeroed already by the memset, remove the explicit
assignments.
Cc: Andreas Faerber <afaerber@suse.de>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target-i386/cpu.c')
| -rw-r--r-- | target-i386/cpu.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target-i386/cpu.c b/target-i386/cpu.c index c04aed929f..79b1bb92f0 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2485,8 +2485,7 @@ static void x86_cpu_reset(CPUState *s) cpu_breakpoint_remove_all(s, BP_CPU); cpu_watchpoint_remove_all(s, BP_CPU); - env->tsc_adjust = 0; - env->tsc = 0; + env->xcr0 = 1; #if !defined(CONFIG_USER_ONLY) /* We hard-wire the BSP to the first CPU. */ |