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authorAndreas Färber <afaerber@suse.de>2012-12-17 06:18:02 +0100
committerAndreas Färber <afaerber@suse.de>2013-01-15 04:09:13 +0100
commit55e5c2850293547203874098f7cec148ffd12dfa (patch)
treef9a9cc316999b7b52726b5186a925022b3747daa /target-i386/cpu.c
parent1b1ed8dc40635d60dd95c04658989af63542fcbf (diff)
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using a negative offset. Therefore the field is placed last in CPUState. Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change. Move common parts of mips cpu_state_reset() to mips_cpu_reset(). Acked-by: Richard Henderson <rth@twiddle.net> (for alpha) [AF: Rebased onto ppc CPU subclasses and openpic changes] Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-i386/cpu.c')
-rw-r--r--target-i386/cpu.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 9f98a41e5c..992b61405f 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1936,7 +1936,7 @@ static void x86_cpu_reset(CPUState *s)
int i;
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
}
@@ -2010,7 +2010,7 @@ static void x86_cpu_reset(CPUState *s)
#if !defined(CONFIG_USER_ONLY)
/* We hard-wire the BSP to the first CPU. */
- if (env->cpu_index == 0) {
+ if (s->cpu_index == 0) {
apic_designate_bsp(env->apic_state);
}
@@ -2148,6 +2148,7 @@ void x86_cpu_realize(Object *obj, Error **errp)
static void x86_cpu_initfn(Object *obj)
{
+ CPUState *cs = CPU(obj);
X86CPU *cpu = X86_CPU(obj);
CPUX86State *env = &cpu->env;
static int inited;
@@ -2179,7 +2180,7 @@ static void x86_cpu_initfn(Object *obj)
x86_cpuid_get_tsc_freq,
x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
- env->cpuid_apic_id = env->cpu_index;
+ env->cpuid_apic_id = cs->cpu_index;
/* init various static tables used in TCG mode */
if (tcg_enabled() && !inited) {