diff options
| author | Rabin Vincent <rabinv@axis.com> | 2016-08-15 13:59:32 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2016-09-28 11:30:59 +0200 |
| commit | ceffd34e8589a9a4f18849a21ae1fecaef3af02e (patch) | |
| tree | 6c66889ab531bb93e0d73a7add944c7dac640e0c /target-cris/cpu.c | |
| parent | 17bc37b75ea4c33a6f36f073a67df687bef840c9 (diff) | |
target-cris: add v17 CPU
In the CRIS v17 CPU an ADDC (add with carry) instruction has been added
compared to the v10 instruction set.
Assembler syntax:
ADDC [Rs],Rd
ADDC [Rs+],Rd
Size: Dword
Description:
The source data is added together with the carry flag to the
destination register. The size of the operation is dword.
Operation:
Rd += s + C-flag;
Flags affected:
S R P U I X N Z V C
- - - - - 0 * * * *
Instruction format: ADDC [Rs],Rd
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs) |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Instruction format: ADDC [Rs+],Rd
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs) |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
[EI: Shorten 80+ lines]
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Rabin Vincent <rabinv@axis.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target-cris/cpu.c')
| -rw-r--r-- | target-cris/cpu.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/target-cris/cpu.c b/target-cris/cpu.c index c5a656bb62..d680cfb52b 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -246,6 +246,16 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = crisv10_cpu_gdb_read_register; } +static void crisv17_cpu_class_init(ObjectClass *oc, void *data) +{ + CPUClass *cc = CPU_CLASS(oc); + CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); + + ccc->vr = 17; + cc->do_interrupt = crisv10_cpu_do_interrupt; + cc->gdb_read_register = crisv10_cpu_gdb_read_register; +} + static void crisv32_cpu_class_init(ObjectClass *oc, void *data) { CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); @@ -273,6 +283,10 @@ static const TypeInfo cris_cpu_model_type_infos[] = { .parent = TYPE_CRIS_CPU, .class_init = crisv11_cpu_class_init, }, { + .name = TYPE("crisv17"), + .parent = TYPE_CRIS_CPU, + .class_init = crisv17_cpu_class_init, + }, { .name = TYPE("crisv32"), .parent = TYPE_CRIS_CPU, .class_init = crisv32_cpu_class_init, |