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authorChristophe Lyon <christophe.lyon@st.com>2011-02-15 13:44:43 +0000
committerAurelien Jarno <aurelien@aurel32.net>2011-02-20 17:43:01 +0100
commitb6c63b9891f0b1415f96e027d5dc8a430c7ec153 (patch)
tree9f8b46ffd8cf08451b0b87132096d376e2297941 /target-arm
parent0670a7b65b0ce122c9f415ac7ae78e015a52a30a (diff)
target-arm: Fix unsigned VRSHL.s8 and .s16 right shifts by type width
Fix handling of unsigned VRSHL.s8 and .s16 right shifts by the type width. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/neon_helper.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/neon_helper.c b/target-arm/neon_helper.c
index 0ddfe6d0a2..52ef994d2b 100644
--- a/target-arm/neon_helper.c
+++ b/target-arm/neon_helper.c
@@ -605,7 +605,7 @@ uint64_t HELPER(neon_rshl_s64)(uint64_t valop, uint64_t shiftop)
tmp < -(ssize_t)sizeof(src1) * 8) { \
dest = 0; \
} else if (tmp == -(ssize_t)sizeof(src1) * 8) { \
- dest = src1 >> (tmp - 1); \
+ dest = src1 >> (-tmp - 1); \
} else if (tmp < 0) { \
dest = (src1 + (1 << (-1 - tmp))) >> -tmp; \
} else { \