diff options
| author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-04-14 21:05:22 +0000 |
|---|---|---|
| committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-04-14 21:05:22 +0000 |
| commit | 827df9f3c5fdea53531acf02b2db0afb9858f053 (patch) | |
| tree | 95cb9c8d0ab76f1155f25df9cda123ce97cb0643 /target-arm | |
| parent | f93eb9ff66868df42f8433d16f2dc48a4af2490f (diff) | |
Add basic OMAP2 chip support.
Add the OMAP242x (arm1136 core) initialisation with basic on-chip
peripherals and update OMAP1 peripherals which are re-used in OMAP2.
Make palmte.c and sd.c errors go to stderr.
Allow disabling SD chipselect.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4213 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/cpu.h | 1 | ||||
| -rw-r--r-- | target-arm/helper.c | 7 |
2 files changed, 8 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 8bf0fcdce2..2ff25a5482 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -373,6 +373,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define ARM_CPUID_PXA270_C0 0x69054114 #define ARM_CPUID_PXA270_C5 0x69054117 #define ARM_CPUID_ARM1136 0x4117b363 +#define ARM_CPUID_ARM1136_R2 0x4107b362 #define ARM_CPUID_ARM11MPCORE 0x410fb022 #define ARM_CPUID_CORTEXA8 0x410fc080 #define ARM_CPUID_CORTEXM3 0x410fc231 diff --git a/target-arm/helper.c b/target-arm/helper.c index b62523b197..f322001d67 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -55,6 +55,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00090078; break; + case ARM_CPUID_ARM1136_R2: case ARM_CPUID_ARM1136: set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_VFP); @@ -206,6 +207,7 @@ static const struct arm_cpu_t arm_cpu_names[] = { { ARM_CPUID_ARM946, "arm946"}, { ARM_CPUID_ARM1026, "arm1026"}, { ARM_CPUID_ARM1136, "arm1136"}, + { ARM_CPUID_ARM1136_R2, "arm1136-r2"}, { ARM_CPUID_ARM11MPCORE, "arm11mpcore"}, { ARM_CPUID_CORTEXM3, "cortex-m3"}, { ARM_CPUID_CORTEXA8, "cortex-a8"}, @@ -1582,6 +1584,7 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) case ARM_CPUID_ARM1026: return 1; case ARM_CPUID_ARM1136: + case ARM_CPUID_ARM1136_R2: return 7; case ARM_CPUID_ARM11MPCORE: return 1; @@ -1762,6 +1765,10 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) case 8: /* TI925T_status */ return 0; } + /* TODO: Peripheral port remap register: + * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt + * controller base address at $rn & ~0xfff and map size of + * 0x200 << ($rn & 0xfff), when MMU is off. */ goto bad_reg; } return 0; |