diff options
| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2016-06-06 16:59:28 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-06-06 16:59:28 +0100 |
| commit | aaa1f954d4cab243e3d5337a72bc6d104e1c4808 (patch) | |
| tree | 809f34f601f6dc8bdfc98c7484717a90c71877f4 /target-arm/translate.h | |
| parent | 2a5a9abd4bc45e2f4c62c77e07aebe53608c6915 (diff) | |
target-arm: A64: Create Instruction Syndromes for Data Aborts
Add support for generating the ISS (Instruction Specific Syndrome) for
Data Abort exceptions taken from AArch64.
These syndromes are used by hypervisors for example to trap and emulate
memory accesses.
We save the decoded data out-of-band with the TBs at translation time.
When exceptions hit, the extra data attached to the TB is used to
recreate the state needed to encode instruction syndromes.
This avoids the need to emit moves with every load/store.
Based on a suggestion from Peter Maydell.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1462464601-10888-2-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate.h')
| -rw-r--r-- | target-arm/translate.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-arm/translate.h b/target-arm/translate.h index 6a18d7badc..dbd7ac83d5 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -59,6 +59,8 @@ typedef struct DisasContext { bool ss_same_el; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; + /* TCG op index of the current insn_start. */ + int insn_start_idx; #define TMP_A64_MAX 16 int tmp_a64_count; TCGv_i64 tmp_a64[TMP_A64_MAX]; |