diff options
| author | Thomas Hanson <thomas.hanson@linaro.org> | 2016-10-17 19:22:18 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-10-17 19:22:18 +0100 |
| commit | 86fb3fa4ed5873b021a362ea26a021f4aeab1bb4 (patch) | |
| tree | 324b6bd80a71a5b3a14a820ef4974874fef37333 /target-arm/translate.h | |
| parent | 08426da7dd0a63835dcf3003e9a022c0d5678be7 (diff) | |
target-arm: Infrastucture changes to enable handling of tagged address loading into PC
When capturing the current CPU state for the TB, extract the TBI0 and TBI1
values from the correct TCR for the current EL and then add them to the TB
flags field.
Then, at the start of code generation for the block, copy the TBI fields
into the DisasContext structure.
Signed-off-by: Thomas Hanson <thomas.hanson@linaro.org>
Message-id: 1476301853-15774-2-git-send-email-thomas.hanson@linaro.org
[PMM: drop useless 'extern' keyword on function prototypes;
provide CONFIG_USER_ONLY trivial versions of arm_regime_tbi[01]()]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate.h')
| -rw-r--r-- | target-arm/translate.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-arm/translate.h b/target-arm/translate.h index dbd7ac83d5..a53f25a407 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -22,6 +22,8 @@ typedef struct DisasContext { int user; #endif ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ + bool tbi0; /* TBI0 for EL0/1 or TBI for EL2/3 */ + bool tbi1; /* TBI1 for EL0/1, not used for EL2/3 */ bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ /* Flag indicating that exceptions from secure mode are routed to EL3. */ |