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authorPeter Maydell <peter.maydell@linaro.org>2011-04-11 16:26:15 +0100
committerAurelien Jarno <aurelien@aurel32.net>2011-04-12 23:33:29 +0200
commit2bc70834e867e7a0c4f30d374405acf8d81bba03 (patch)
tree1f749fafef5848d5d26e4c33ee438ace644ffa33 /target-arm/translate.c
parentcc13115bdecb4596fd4201f16455220a7d1a85f8 (diff)
target-arm: Collapse VSRI case into VSHL, VSLI
Collapse some switch cases for VSRI into those for VSHL, VSLI, since the bodies are the same. (This is not completely obvious for the size < 3 case, but since for VSRI we know U=1 the GEN_NEON_INTEGER_OP() expansion is equivalent to the open-coded VSHL/VSLI case.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r--target-arm/translate.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index c0ffa9fca8..a86c54c564 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4813,8 +4813,6 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
break;
case 4: /* VSRI */
- gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
- break;
case 5: /* VSHL, VSLI */
gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
break;
@@ -4867,8 +4865,6 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
GEN_NEON_INTEGER_OP(rshl);
break;
case 4: /* VSRI */
- GEN_NEON_INTEGER_OP(shl);
- break;
case 5: /* VSHL, VSLI */
switch (size) {
case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;