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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-07-06 10:05:44 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-07-06 10:05:44 +0100 |
| commit | c87e5a61c2b3024116f52f7e68273f864ff7ab82 (patch) | |
| tree | d38337c781c9c343ccf97520db47a941167c8d0d /target-arm/translate.c | |
| parent | 049e24a191c212d9468db84169197887f2c91586 (diff) | |
target-arm: Implement YIELD insn to yield in ARM and Thumb translators
Implement the YIELD instruction in the ARM and Thumb translators to
actually yield control back to the top level loop rather than being
a simple no-op. (We already do this for A64.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1435672316-3311-3-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 971b6db061..69ac18c108 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4080,6 +4080,10 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr) static void gen_nop_hint(DisasContext *s, int val) { switch (val) { + case 1: /* yield */ + gen_set_pc_im(s, s->pc); + s->is_jmp = DISAS_YIELD; + break; case 3: /* wfi */ gen_set_pc_im(s, s->pc); s->is_jmp = DISAS_WFI; @@ -11459,6 +11463,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, case DISAS_WFE: gen_helper_wfe(cpu_env); break; + case DISAS_YIELD: + gen_helper_yield(cpu_env); + break; case DISAS_SWI: gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), default_exception_el(dc)); |