diff options
| author | Peter Crosthwaite <peter.crosthwaite@petalogix.com> | 2012-10-16 19:15:50 +1000 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2012-10-17 19:56:46 +0200 |
| commit | b6348f29d033d5a8a26f633d2ee94362595f32a4 (patch) | |
| tree | 46e3548993a2df3231b8ef5d5c087fa72e54f934 /target-arm/translate.c | |
| parent | 1414968a6aecd23cb037bc9e718d6f05ead2afaf (diff) | |
target-arm/translate: Fix RRX operands
Instructions that both use the RRX second operand and update CS were
incorrect, as the Carry flag was updated too early. An example of such an
instruction would be:
ands r12,r13,RRX
Ands, because of the "s" flag will update the carry flag. But the RRX second
operand rotates through the C flag which should happen before the update.
Fixed the ordering of the two, the old carry is read by "r13,RRX" before being
updated.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reported-by: Vinesh Peringat <vineshp@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index c6840b7832..daccb15c23 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -516,10 +516,10 @@ static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags) tcg_gen_rotri_i32(var, var, shift); break; } else { TCGv tmp = tcg_temp_new_i32(); + tcg_gen_shli_i32(tmp, cpu_CF, 31); if (flags) shifter_out_im(var, 0); tcg_gen_shri_i32(var, var, 1); - tcg_gen_shli_i32(tmp, cpu_CF, 31); tcg_gen_or_i32(var, var, tmp); tcg_temp_free_i32(tmp); } |