diff options
| author | Peter Chubb <peter.chubb@nicta.com.au> | 2013-04-19 12:24:18 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-04-19 12:24:18 +0100 |
| commit | 3b3284486be6898937395fac3ddbd2e68c5cb52f (patch) | |
| tree | 52b58b6c781d25cc82b152b7ca6b436f29f4c476 /target-arm/translate.c | |
| parent | 09dada400328d75daf79e3eca1e48e024fec148d (diff) | |
target-arm: Reinsert missing return statement in ARM mode SRS decode
Since patch
81465888c5306cd94abb9847e560796fd13d3c2f
target-arm: factor out handling of SRS instruction
the ARM mode SRS instruction has not worked in QEMU.
The problem is a missing return directive that was removed in the
refactoring, so after decoding the instruction, qemu would fall through
to generate an UNDEF exception for an illegal instruction.
Signed-off-by: Peter Chubb <peter.chubb@nicta.com.au>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 35a21be931..a1b7b8c1a8 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6762,6 +6762,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) } ARCH(6); gen_srs(s, (insn & 0x1f), (insn >> 23) & 3, insn & (1 << 21)); + return; } else if ((insn & 0x0e50ffe0) == 0x08100a00) { /* rfe */ int32_t offset; |