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authorBlue Swirl <blauwirbel@gmail.com>2012-09-04 20:25:59 +0000
committerBlue Swirl <blauwirbel@gmail.com>2012-09-15 17:44:32 +0000
commitd31dd73e48561de5f9d718febfb44224f7aab818 (patch)
treefef4014b287bcdb3c1085663d1a375160f6c6069 /target-arm/translate.c
parent9ef392772597693b07959460f6c27b9b5a8287a1 (diff)
target-arm: final conversion to AREG0 free mode
Convert code load functions and switch to AREG0 free mode. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r--target-arm/translate.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 9ae3b26aa6..f4b447a49a 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6534,7 +6534,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
TCGv addr;
TCGv_i64 tmp64;
- insn = arm_ldl_code(s->pc, s->bswap_code);
+ insn = arm_ldl_code(env, s->pc, s->bswap_code);
s->pc += 4;
/* M variants do not implement ARM mode. */
@@ -7962,7 +7962,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
/* Fall through to 32-bit decode. */
}
- insn = arm_lduw_code(s->pc, s->bswap_code);
+ insn = arm_lduw_code(env, s->pc, s->bswap_code);
s->pc += 2;
insn |= (uint32_t)insn_hw1 << 16;
@@ -8992,7 +8992,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
}
}
- insn = arm_lduw_code(s->pc, s->bswap_code);
+ insn = arm_lduw_code(env, s->pc, s->bswap_code);
s->pc += 2;
switch (insn >> 12) {