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authorPeter Maydell <peter.maydell@linaro.org>2011-01-14 20:39:19 +0100
committerAurelien Jarno <aurelien@aurel32.net>2011-01-14 20:39:19 +0100
commit5de3a9d3b72a9aebc126caee95fe515a900130bf (patch)
treef5e5eb21093e5438eb79b2b3146f8c40d1f87824 /target-arm/translate.c
parent61f74d6a290d606504e4fbd6a94cbee3ce277533 (diff)
target-arm: Remove redundant setting of IT bits before Thumb SWI
Remove a redundant call to gen_set_condexec() in the translation of Thumb mode SWI. (SWI and WFI generate "exceptions" which happen after the execution of the instruction, ie when PC and IT bits have updated. So the condexec bits at this point are not correct. However, the code that handles finishing the translation of the TB will write the correct value of the condexec bits later, so the only effect was that a conditional Thumb SWI would generate slightly worse code than necessary.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r--target-arm/translate.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 10bd54522d..74b9657b9a 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9016,7 +9016,6 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s)
if (cond == 0xf) {
/* swi */
- gen_set_condexec(s);
gen_set_pc_im(s->pc);
s->is_jmp = DISAS_SWI;
break;