diff options
| author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-04-13 00:57:49 +0000 |
|---|---|---|
| committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-04-13 00:57:49 +0000 |
| commit | 6c95676b16dcabd69ad9a57c0a9ec4878d3d0e3d (patch) | |
| tree | 048ea12772b8028343aa95ae9297e43746b06fdc /target-arm/translate.c | |
| parent | 6f9bc132639d8d3349581441daa4f799c28d48fb (diff) | |
Store the right TCG temp (typo).
Stops ARMv6 target from segfaulting early.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4201 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 9ff3ff8161..f1695decdf 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6372,7 +6372,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) break; case 1: if ((insn & 0x00700020) == 0) { - /* Hafword pack. */ + /* Halfword pack. */ tmp = load_reg(s, rn); tmp2 = load_reg(s, rm); shift = (insn >> 7) & 0x1f; @@ -6455,7 +6455,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) dead_tmp(tmp2); } } - store_reg(s, rd, tmp2); + store_reg(s, rd, tmp); } else if ((insn & 0x003f0f60) == 0x003f0f20) { /* rev */ tmp = load_reg(s, rm); |