diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2010-12-27 19:54:49 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-12-27 19:56:43 +0100 |
| commit | 1a855029af40df40144a322bba0e1e61c68eed2a (patch) | |
| tree | e90493fd1888484cdf7f1e6f91d8acf4a5d00673 /target-arm/translate.c | |
| parent | 5697f6ae4183f3b3320a1fe677e3404a05e75783 (diff) | |
target-arm: fix bug in translation of REVSH
The translation of REVSH shifted the low byte 8 steps left before performing
an 8-bit sign extend, causing this part of the expression to alwas be 0.
Reported-by: Johan Bengtsson <teofrastius@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index d4a0666be5..24b4fb65ed 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -250,13 +250,9 @@ static void gen_rev16(TCGv var) /* Byteswap low halfword and sign extend. */ static void gen_revsh(TCGv var) { - TCGv tmp = new_tmp(); - tcg_gen_shri_i32(tmp, var, 8); - tcg_gen_andi_i32(tmp, tmp, 0x00ff); - tcg_gen_shli_i32(var, var, 8); - tcg_gen_ext8s_i32(var, var); - tcg_gen_or_i32(var, var, tmp); - dead_tmp(tmp); + tcg_gen_ext16u_i32(var, var); + tcg_gen_bswap16_i32(var, var); + tcg_gen_ext16s_i32(var, var); } /* Unsigned bitfield extract. */ |