diff options
| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-12-18 16:55:25 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-12-18 16:55:25 +0000 |
| commit | 68998c5de3b92e7034aa9d8fecf53f0bc3ccc91e (patch) | |
| tree | 941a8f9161b7288a73ed5a1ec1f43f5387a036bf /target-arm/translate.c | |
| parent | 6d7e63262c7e47400c37cb6b789b1e2df8d492e4 (diff) | |
cpu_reset() fix (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1712 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index a5eb3b4c72..089fbf2fd9 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2431,10 +2431,10 @@ int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) void cpu_reset(CPUARMState *env) { #if defined (CONFIG_USER_ONLY) + env->uncached_cpsr = ARM_CPU_MODE_USR; +#else /* SVC mode with interrupts disabled. */ env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; -#else - env->uncached_cpsr = ARM_CPU_MODE_USR; #endif env->regs[15] = 0; } |