diff options
| author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-04-20 01:03:45 +0000 |
|---|---|---|
| committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-04-20 01:03:45 +0000 |
| commit | 601d70b9e5dea95a3854ba801672786f40230b75 (patch) | |
| tree | 3022f114b75454606ba1c5451844b0f29d4e86c0 /target-arm/translate.c | |
| parent | 66230e0dee3f29107402d25f2f867006ea5f593f (diff) | |
Remove an unused field and fix some non-code typos.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4222 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index e849b7fc3f..59158b3c7c 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2877,7 +2877,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) tmp = load_cpu_field(vfp.xregs[rn]); break; case ARM_VFP_FPSCR: - if (rd == 15) { + if (rd == 15) { tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); tcg_gen_andi_i32(tmp, tmp, 0xf0000000); } else { @@ -6887,7 +6887,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) if (!(arm_feature(env, ARM_FEATURE_THUMB2) || arm_feature (env, ARM_FEATURE_M))) { - /* Thumb-1 cores may need to tread bl and blx as a pair of + /* Thumb-1 cores may need to treat bl and blx as a pair of 16-bit instructions to get correct prefetch abort behavior. */ insn = insn_hw1; if ((insn & (1 << 12)) == 0) { |