diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2014-06-19 18:06:24 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-06-19 18:06:24 +0100 |
| commit | 220ad4ca846d8e0734dd2d2af38c61a6f5436d66 (patch) | |
| tree | 8da0f55114792351149b2999ebf0dc04c8f62f83 /target-arm/translate-a64.c | |
| parent | 5661ae6be23d8831a19c82f8eafb2aaecdf2da6a (diff) | |
target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int()
In disas_simd_3same_int(), none of the instructions permit is_q
to be false with size == 3 (this would be a vector operation with
a one-element vector, and the instruction set encodes those as
scalar operations). Replace the always-true ?: check with an
assert.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1402171881-14343-3-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/translate-a64.c')
| -rw-r--r-- | target-arm/translate-a64.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 63ad787e9f..cbc8a3574d 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -9052,7 +9052,8 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) } if (size == 3) { - for (pass = 0; pass < (is_q ? 2 : 1); pass++) { + assert(is_q); + for (pass = 0; pass < 2; pass++) { TCGv_i64 tcg_op1 = tcg_temp_new_i64(); TCGv_i64 tcg_op2 = tcg_temp_new_i64(); TCGv_i64 tcg_res = tcg_temp_new_i64(); |