diff options
| author | Greg Bellows <greg.bellows@linaro.org> | 2014-10-24 12:19:14 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-10-24 12:19:14 +0100 |
| commit | dcbff19bd07c198f4f9bdbf2db740a8e282dd5f6 (patch) | |
| tree | a304e8bdf598a72b540eb0b84ab4bca496b7f4d3 /target-arm/translate-a64.c | |
| parent | 027fc52704b815bd67a92399d255f066308ca70c (diff) | |
target-arm: rename arm_current_pl to arm_current_el
Renamed the arm_current_pl CPU function to more accurately represent that it
returns the ARMv8 EL rather than ARMv7 PL.
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1413910544-20150-5-git-send-email-greg.bellows@linaro.org
[PMM: fixed a minor merge resolution error in a couple of hunks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate-a64.c')
| -rw-r--r-- | target-arm/translate-a64.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index b15261b381..3a3c48acf4 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1226,7 +1226,7 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, int op = op1 << 3 | op2; switch (op) { case 0x05: /* SPSel */ - if (s->current_pl == 0) { + if (s->current_el == 0) { unallocated_encoding(s); return; } @@ -1323,7 +1323,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, } /* Check access permissions */ - if (!cp_access_ok(s->current_pl, ri, isread)) { + if (!cp_access_ok(s->current_el, ri, isread)) { unallocated_encoding(s); return; } @@ -1362,7 +1362,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, * guaranteed to be constant by the tb flags. */ tcg_rt = cpu_reg(s, rt); - tcg_gen_movi_i64(tcg_rt, s->current_pl << 2); + tcg_gen_movi_i64(tcg_rt, s->current_el << 2); return; case ARM_CP_DC_ZVA: /* Writes clear the aligned block of memory which rt points into. */ @@ -1485,7 +1485,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16)); break; case 2: - if (s->current_pl == 0) { + if (s->current_el == 0) { unallocated_encoding(s); break; } @@ -1498,7 +1498,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16)); break; case 3: - if (s->current_pl == 0) { + if (s->current_el == 0) { unallocated_encoding(s); break; } @@ -1575,7 +1575,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); break; case 4: /* ERET */ - if (s->current_pl == 0) { + if (s->current_el == 0) { unallocated_encoding(s); return; } @@ -10930,7 +10930,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = cpu->cp_regs; - dc->current_pl = arm_current_pl(env); + dc->current_el = arm_current_el(env); dc->features = env->features; /* Single step state. The code-generation logic here is: @@ -10951,7 +10951,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, dc->ss_active = ARM_TBFLAG_AA64_SS_ACTIVE(tb->flags); dc->pstate_ss = ARM_TBFLAG_AA64_PSTATE_SS(tb->flags); dc->is_ldex = false; - dc->ss_same_el = (arm_debug_target_el(env) == dc->current_pl); + dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); init_tmp_a64_array(dc); |