diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2014-04-15 19:18:41 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:34:04 +0100 |
commit | aca3f40b374428e9c01068cf96294483cbb760a0 (patch) | |
tree | ea0528c089b29a84a44cac1cd539d80917e51308 /target-arm/translate-a64.c | |
parent | 9225d739e7f6ec8d2139f79c3d2e3282cc725364 (diff) |
target-arm: A64: Implement DC ZVA
Implement the DC ZVA instruction, which clears a block of memory.
The fast path obtains a pointer to the underlying RAM via the TCG TLB
data structure so we can do a direct memset(), with fallback to a
simple byte-store loop in the slow path.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/translate-a64.c')
-rw-r--r-- | target-arm/translate-a64.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 0ec2f65586..4c5402a0f7 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1335,6 +1335,11 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, tcg_rt = cpu_reg(s, rt); tcg_gen_movi_i64(tcg_rt, s->current_pl << 2); return; + case ARM_CP_DC_ZVA: + /* Writes clear the aligned block of memory which rt points into. */ + tcg_rt = cpu_reg(s, rt); + gen_helper_dc_zva(cpu_env, tcg_rt); + return; default: break; } |