diff options
| author | Richard Henderson <rth@twiddle.net> | 2015-09-17 14:25:46 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2015-10-07 20:36:27 +1100 |
| commit | 959082fc4a93a016a6b697e1e0c2b373d8a3a373 (patch) | |
| tree | dda759b30da56f02813c9328372a4af3b23c0cb0 /target-arm/translate-a64.c | |
| parent | 667b8e29c5b1d8c5b4e6ad5f780ca60914eb6e96 (diff) | |
target-*: Increment num_insns immediately after tcg_gen_insn_start
This does tidy the icount test common to all targets.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-arm/translate-a64.c')
| -rw-r--r-- | target-arm/translate-a64.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 6a66ac019a..4670941084 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -11104,8 +11104,9 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(dc->pc); + num_insns++; - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -11120,7 +11121,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns == 0); + assert(num_insns == 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); dc->is_jmp = DISAS_EXC; @@ -11139,7 +11140,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - num_insns++; } while (!dc->is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled && !singlestep && |