diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2015-02-13 11:44:49 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-02-13 11:44:50 +0000 |
| commit | cd2d5541271f1934345d8ca42f5fafff1744eee7 (patch) | |
| tree | 502c45c44d0537fca5e576da33898a7f5eaf9f01 /target-arm/translate-a64.c | |
| parent | e344e7afc1a04ab11c843c069cef0cdcc1c7787e (diff) | |
| parent | 15fc7daa770764cc795158cbb525569f156f3659 (diff) | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150212' into staging
Convert to linked list.
# gpg: Signature made Fri 13 Feb 2015 05:40:41 GMT using RSA key ID 4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg: aka "Richard Henderson <rth@redhat.com>"
# gpg: aka "Richard Henderson <rth@twiddle.net>"
* remotes/rth/tags/pull-tcg-20150212:
tcg: Remove unused opcodes
tcg: Implement insert_op_before
tcg: Remove opcodes instead of noping them out
tcg: Put opcodes in a linked list
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
tcg: Move emit of INDEX_op_end into gen_tb_end
tcg: Reduce ifdefs in tcg-op.c
tcg: Move some opcode generation functions out of line
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate-a64.c')
| -rw-r--r-- | target-arm/translate-a64.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 9f54501a9e..34b489f2ec 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -10920,7 +10920,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, CPUARMState *env = &cpu->env; DisasContext dc1, *dc = &dc1; CPUBreakpoint *bp; - uint16_t *gen_opc_end; int j, lj; target_ulong pc_start; target_ulong next_page_start; @@ -10931,8 +10930,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, dc->tb = tb; - gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; - dc->is_jmp = DISAS_NEXT; dc->pc = pc_start; dc->singlestep_enabled = cs->singlestep_enabled; @@ -11002,7 +10999,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, } if (search_pc) { - j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; + j = tcg_op_buf_count(); if (lj < j) { lj++; while (lj < j) { @@ -11052,7 +11049,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, * ensures prefetch aborts occur at the right place. */ num_insns++; - } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end && + } while (!dc->is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled && !singlestep && !dc->ss_active && @@ -11112,7 +11109,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, done_generating: gen_tb_end(tb, num_insns); - *tcg_ctx.gen_opc_ptr = INDEX_op_end; #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { @@ -11124,7 +11120,7 @@ done_generating: } #endif if (search_pc) { - j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; + j = tcg_op_buf_count(); lj++; while (lj <= j) { tcg_ctx.gen_opc_instr_start[lj++] = 0; |