diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2016-02-18 14:16:16 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2016-02-18 14:16:16 +0000 |
commit | f2cae6092767aaf418778eada15be444c23883be (patch) | |
tree | c865749fe752317d18af34713b3aa19c653b0de6 /target-arm/op_helper.c | |
parent | d6c8cf815171e35e0b1ef4e0cff602ab3d575747 (diff) |
target-arm: Report correct syndrome for FPEXC32_EL2 traps
If access to FPEXC32_EL2 is trapped by CPTR_EL2.TFP or CPTR_EL3.TFP,
this should be reported with a syndrome register indicating an
FP access trap, not one indicating a system register access trap.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Diffstat (limited to 'target-arm/op_helper.c')
-rw-r--r-- | target-arm/op_helper.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 4c0980e5a5..049b52158b 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -500,6 +500,19 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome, target_el = 3; syndrome = syn_uncategorized(); break; + case CP_ACCESS_TRAP_FP_EL2: + target_el = 2; + /* Since we are an implementation that takes exceptions on a trapped + * conditional insn only if the insn has passed its condition code + * check, we take the IMPDEF choice to always report CV=1 COND=0xe + * (which is also the required value for AArch64 traps). + */ + syndrome = syn_fp_access_trap(1, 0xe, false); + break; + case CP_ACCESS_TRAP_FP_EL3: + target_el = 3; + syndrome = syn_fp_access_trap(1, 0xe, false); + break; default: g_assert_not_reached(); } |