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author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-09-16 21:08:06 +0000 |
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committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-09-16 21:08:06 +0000 |
commit | 5fafdf24ef2c090c164d4dc89684b3f379dbdd87 (patch) | |
tree | c0654ee63b6dac76d98b427e92ef16850a90c652 /target-arm/nwfpe/fpsr.h | |
parent | bd494f4cbd4187dda8cc8f4739763f24a31a4c8b (diff) |
find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/nwfpe/fpsr.h')
-rw-r--r-- | target-arm/nwfpe/fpsr.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-arm/nwfpe/fpsr.h b/target-arm/nwfpe/fpsr.h index 6dafb0f524..0c665431eb 100644 --- a/target-arm/nwfpe/fpsr.h +++ b/target-arm/nwfpe/fpsr.h @@ -30,7 +30,7 @@ one byte. EXCEPTION TRAP ENABLE BYTE SYSTEM CONTROL BYTE CUMULATIVE EXCEPTION FLAGS BYTE - + The FPCR is a 32 bit register consisting of bit flags. */ @@ -43,7 +43,7 @@ typedef unsigned int FPCR; /* type for floating point control register */ #define MASK_SYSID 0xff000000 #define BIT_HARDWARE 0x80000000 -#define FP_EMULATOR 0x01000000 /* System ID for emulator */ +#define FP_EMULATOR 0x01000000 /* System ID for emulator */ #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */ /* EXCEPTION TRAP ENABLE BYTE |