diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2016-02-23 15:36:43 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-02-26 15:09:41 +0000 |
| commit | f8c88bbcda76d5674e4bb125471371b41d330df8 (patch) | |
| tree | 94a6ea0437de3b0629eba23dd6dde4e0e38a743c /target-arm/machine.c | |
| parent | 50866ba5a2cfe922aaf3edb79f6eac5b0653477a (diff) | |
target-arm: Raw CPSR writes should skip checks and bank switching
Raw CPSR writes should skip the architectural checks for whether
we're allowed to set the A or F bits and should also not do
the switching of register banks if the mode changes. Handle
this inside cpsr_write(), which allows us to drop the "manually
set the mode bits to avoid the bank switch" code from all the
callsites which are using CPSRWriteRaw.
This fixes a bug in 32-bit KVM handling where we had forgotten
the "manually set the mode bits" part and could thus potentially
trash the register state if the mode from the last exit to userspace
differed from the mode on this exit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1455556977-3644-4-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/machine.c')
| -rw-r--r-- | target-arm/machine.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/target-arm/machine.c b/target-arm/machine.c index 0fc7df0ee2..03a73d950e 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -173,8 +173,6 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size) return 0; } - /* Avoid mode switch when restoring CPSR */ - env->uncached_cpsr = val & CPSR_M; cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); return 0; } |