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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:37:26 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:37:26 +0100 |
| commit | 2d03b49c3f225994c4b0b46146437d8c887d6774 (patch) | |
| tree | 00663246afe656b777e3c218cfea25e7ed32ffc2 /target-arm/helper.h | |
| parent | c6138aabfb2a8769392d605dc1e339b3095aab6a (diff) | |
| parent | e44a90c59697cf98e05619fbb6f77a403d347495 (diff) | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140417-1' into staging
target-arm queue:
* AArch64 system mode support; this is all the CPU emulation code
but not the virt board support
* cadence_ttc match register bugfix
* Allwinner A10 PIC, PIT and ethernet fixes
[with update to avoid duplicate typedef]
* zynq-slcr rewrite
* cadence_gem bugfix
* fix for SMLALD/SMLSLD insn in A32
* fix for SQXTUN in A64
# gpg: Signature made Thu 17 Apr 2014 21:35:57 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
* remotes/pmaydell/tags/pull-target-arm-20140417-1: (51 commits)
target-arm: A64: fix unallocated test of scalar SQXTUN
arm: translate.c: Fix smlald Instruction
net: cadence_gem: Make phy respond to broadcast
misc: zynq_slcr: Make DB_PRINTs always compile
misc: zynq_slcr: Convert SBD::init to object init
misc: zynq-slcr: Rewrite
allwinner-emac: update irq status after writes to interrupt registers
allwinner-emac: set autonegotiation complete bit on link up
allwinner-a10-pit: implement prescaler and source selection
allwinner-a10-pit: use level triggered interrupts
allwinner-a10-pit: avoid generation of spurious interrupts
allwinner-a10-pic: fix behaviour of pending register
allwinner-a10-pic: set vector address when an interrupt is pending
timer: cadence_ttc: Fix match register write logic
target-arm/gdbstub64.c: remove useless 'break' statement.
target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32
target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc
target-arm: Make Cortex-A15 CBAR read-only
target-arm: Implement CBAR for Cortex-A57
target-arm: Implement Cortex-A57 implementation-defined system registers
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/helper.h')
| -rw-r--r-- | target-arm/helper.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/target-arm/helper.h b/target-arm/helper.h index 366c1b3ea5..a5449e7b6f 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -48,7 +48,8 @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) -DEF_HELPER_2(exception, void, env, i32) +DEF_HELPER_2(exception_internal, void, env, i32) +DEF_HELPER_3(exception_with_syndrome, void, env, i32, i32) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(wfe, void, env) @@ -58,13 +59,14 @@ DEF_HELPER_1(cpsr_read, i32, env) DEF_HELPER_3(v7m_msr, void, env, i32, i32) DEF_HELPER_2(v7m_mrs, i32, env, i32) -DEF_HELPER_2(access_check_cp_reg, void, env, ptr) +DEF_HELPER_3(access_check_cp_reg, void, env, ptr, i32) DEF_HELPER_3(set_cp_reg, void, env, ptr, i32) DEF_HELPER_2(get_cp_reg, i32, env, ptr) DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) DEF_HELPER_2(get_cp_reg64, i64, env, ptr) DEF_HELPER_3(msr_i_pstate, void, env, i32, i32) +DEF_HELPER_1(exception_return, void, env) DEF_HELPER_2(get_r13_banked, i32, env, i32) DEF_HELPER_3(set_r13_banked, void, env, i32, i32) @@ -514,6 +516,7 @@ DEF_HELPER_4(crypto_aesmc, void, env, i32, i32, i32) DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) +DEF_HELPER_2(dc_zva, void, env, i64) #ifdef TARGET_AARCH64 #include "helper-a64.h" |