diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2012-03-14 12:26:10 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-03-15 17:00:52 +0000 |
| commit | c98d174c24b915e9908785feb63eb3b5abe33818 (patch) | |
| tree | d0630eec1485a82d7c841dc65765ffde948fae11 /target-arm/helper.c | |
| parent | 4de47793d49e70ee048e15889d4bf139e7b36ce7 (diff) | |
target-arm: Clear IT bits when taking exceptions in v7M
When taking an exception for an M profile core, we must clear
the IT bits. Since the IT bits are cached in env->condexec_bits
we must clear them there: writing the bits in env->uncached_cpsr
has no effect. (Reported as LP:944645.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/helper.c')
| -rw-r--r-- | target-arm/helper.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 4116feebf5..1314f23d59 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -877,7 +877,8 @@ static void do_interrupt_v7m(CPUARMState *env) v7m_push(env, env->regs[1]); v7m_push(env, env->regs[0]); switch_v7m_sp(env, 0); - env->uncached_cpsr &= ~CPSR_IT; + /* Clear IT bits */ + env->condexec_bits = 0; env->regs[14] = lr; addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4); env->regs[15] = addr & 0xfffffffe; |